RS=DETACH, RST=RESETCOMPLETE
USB command (device mode)
| RS | Run/Stop 0 (DETACH): Writing a 0 to this bit will cause a detach event. 1 (ATACH): Writing a one to this bit will cause the device controller to enable a pull-up on USB_DP and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the device controller has been properly initialized. |
| RST | Controller reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 0 (RESETCOMPLETE): Set to 0 by hardware when the reset process is complete. 1 (RESET): When software writes a one to this bit, the Device Controller resets its internal pipelines, timers, counters, state machines etc. to their initial values. Writing a one to this bit when the device is in the attached state is not recommended, since the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. |
| RESERVED | Not used in device mode. |
| RESERVED | Not used in device mode. |
| RESERVED | Not used in device mode. |
| RESERVED | Not used in device mode. Writing a one to this bit when the device mode is selected, will have undefined results. |
| RESERVED | Reserved. These bits should be set to 0. |
| RESERVED | Not used in Device mode. |
| RESERVED | Reserved.These bits should be set to 0. |
| RESERVED | Not used in Device mode. |
| RESERVED | Reserved.These bits should be set to 0. |
| SUTW | Setup trip wire During handling a setup packet, this bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (see USBMODE register) then there exists a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software and will be cleared by hardware when a hazard exists. (See Section 18.10). |
| ATDTW | Add dTD trip wire This bit is used as a semaphore to ensure the to proper addition of a new dTD to an active (primed) endpoint’s linked list. This bit is set and cleared by software during the process of adding a new dTD. See also Section 18.10. This bit shall also be cleared by hardware when its state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized. |
| FS2 | Not used in device mode. |
| ITC | Interrupt threshold control. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. All other values are reserved. 0x0 = Immediate (no threshold) 0x1 = 1 micro frame. 0x2 = 2 micro frames. 0x8 = 8 micro frames. 0x10 = 16 micro frames. 0x20 = 32 micro frames. 0x40 = 64 micro frames. |
| RESERVED | Reserved |